tangxifan · Sep 16, 2026 · Sep 16, 2026 · Sep 18, 2026 · Sep 25, 2026 · Oct 1, 2026
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -136,10 +136,10 @@ jobs:
       - name: ccache
         uses: hendrikmuhs/ccache-action@v1.2
         with:
-          key: ${{ runner.os }}-msys2-${{ github.job }}-${{ matrix.config.prefix }}-${{ hashFiles('**/CMakeLists.txt', '**/Makefile') }}
+          key: ${{ runner.os }}-macos-${{ github.job }}-${{ matrix.config.prefix }}-${{ hashFiles('**/CMakeLists.txt', '**/Makefile') }}
           restore-keys: |
-            ${{ runner.os }}-msys2-${{ github.job }}-${{ matrix.config.prefix }}-
-            ${{ runner.os }}-msys2-${{ github.job }}-
+            ${{ runner.os }}-macos-${{ github.job }}-${{ matrix.config.prefix }}-
+            ${{ runner.os }}-macos-${{ github.job }}-
 
       - name: Get number of CPU cores
         uses: SimenB/github-actions-cpu-cores@v3

diff --git a/.gitmodules b/.gitmodules
@@ -4,3 +4,6 @@
 [submodule "vtr-verilog-to-routing"]
 	path = vtr-verilog-to-routing
 	url = https://github.com/verilog-to-routing/vtr-verilog-to-routing.git
+[submodule "openfpga_flow/benchmarks/ubm"]
+	path = openfpga_flow/benchmarks/ubm
+	url = https://github.com/tangxifan/ubm
diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_hour.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_minute.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_second.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_three_tb.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v b/openfpga_flow/benchmarks/micro_benchmark/FSM_three_code/FSM_top.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/ALU.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/ALU.v