Use submodule: ubm

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue: Multi-clock benchmark suites #2721
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

As stated in #2721

What does this pull request change?

This PR improves in the following aspects:

• Now microbenchmark directory is removed
• Use ubm as a submodule
• Correct all the task configuration to use ubm files.
• Added a script to update all the task configuration files

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.