Deflection-Routed Butterfly Fat Trees on FPGAs

This repository contains the Verilog RTL, simulation harnesses, and analysis scripts for the paper:

Nachiket Kapre, “Deflection-Routed Butterfly Fat Trees on FPGAs,” 27th International Conference on Field-Programmable Logic and Applications (FPL), 2017.

Read the paper

The design implements bufferless, deflection-routed butterfly fat-tree (BFT) networks with localized deflections. The repository also includes scripts and archived results used to study throughput, latency, area, traffic patterns, and Rent-parameter tradeoffs.

Requirements

• Icarus Verilog with SystemVerilog support
• A POSIX-compatible shell
• R, if you want to regenerate the analysis plots

Build and simulate

make

The default target compiles the RTL with Icarus Verilog and runs the original large stress simulation, writing its verbose output to tmp/test.log. Depending on the machine, this simulation can take a long time and produce a multi-gigabyte log. To verify compilation without running it:

make a.out

After a completed simulation, compare sent and received packet identifiers with:

./check.sh

The historical sweep and plotting scripts are preserved as research artifacts; some encode assumptions about the original tool environment and may require local adaptation.

Repository status

This is an archival release of the code accompanying the 2017 paper. A later, flow-controlled BFT implementation is available in watcag/bft-flow.