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[#941] NVIC: Implement ICSR RETTOBASE - #217

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[#941] NVIC: Implement ICSR RETTOBASE#217
PhysicistJohn wants to merge 1 commit into
renode:masterfrom
PhysicistJohn:941-nvic_rettobase

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Related issue

Fixes renode/renode#941

Description

Implements the read-only ICSR.RETTOBASE bit for Armv7-M and Armv8-M cores.

The bit is set when there are zero or one active exceptions and clear when
there are nested active exceptions. Cortex-M0, Cortex-M0+, and Cortex-M1 keep
bit 11 at zero because Armv6-M reserves it.

The explicit model check is needed because Renode currently exposes Armv7
compatibility features for the Cortex-M0 family.

Regression tests cover zero, one, and two active exceptions.

Usage example

The reproduction from renode/renode#941 now reports bit 11 set for an idle
Cortex-M4 NVIC. A native matrix also verifies every currently supported
Cortex-M model.

Additional information

Validated on macOS Arm64 with .NET 8:

  • targeted NVIC tests: 3 passed
  • full managed solution: 1,114 passed, 17 existing skips, 0 failures
  • dotnet format --verify-no-changes: passed
  • native Cortex-M0/M0+/M1/M3/M4/M4F/M7/M23/M33/M52/M55/M85 matrix: passed

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CLAassistant commented Jul 11, 2026

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NVIC: ICSR.RETTOBASE always reads zero

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