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ArchSem-Lean
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This is a Lean port of ArchSem-Rocq [1], a framework for formally
defining the specification of multi-threaded computer architectures
in a way suitable for formal verification or execution on small litmus
tests. The ISA semantics are generated from a Sail [2] specification,
memory concurrency models are implemented in this repository.

[1] https://github.com/rems-project/archsem
[2] https://github.com/rems-project/sail

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