Dual Core Baremetal Setup

[bantierr]

Hi,

I have a question related to #175. I am also trying to get a dual core setup of Cheshire working for bare-metal simulation. I am targeting a setup that uses the CLINT.
I applied the changes I mentioned in the issue #175, but after some testing, the cache-coherence does not seem to work. Is there a working dual-core setup of Cheshire available, or did I forget something ?
From what I found out, this issue: https://pulp-platform.org/community/showthread.php?tid=359 seems to mention a working dual-core setup, and the Carfield project also seems to use a dual core configuration of Cheshire.

Any help would be appreciated, if such a configuration is possible and available,
Best,
Quentin

[anythingtemp8]

Hi Quentin,
I faced the same issue sometime ago and had to drop cheshire as a multicore SoC for my research work.
The conclusion from my testing was, something in the bootloader relevant to SMP is blocking the system to boot properly when used in multicore config. However, you should be able to run baremetal programs (I did on HW using OpenOCD+GDB). I could target each core individually by changing the core id to 0 or 1 respectively.

cheshire/util/openocd.common.tcl

Line 16 in d816ac2

target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0

I really hope someone from the devs would step in to figure it out

[bantierr]

Hey, thanks for the answer :) Yes, I saw, I am the one who answer to the thread on #175 a few weeks ago. I can run bare metal programs on two cores, but it seems that the setup right now is not coherent, so I cannot communicate between core using memory.

I also pretty much gave up in using a multicore setup in my project, but I found this thread on the pulp forum: https://pulp-platform.org/community/showthread.php?tid=359 where a main researcher of the lab mentions that a dual core setup exists, so I figured I would ask again, but for bare-metal instead of Linux.

lets see, maybe something comes up,
Best,
Quentin

[anythingtemp8]

Hi,
I found there was a culsans branch (which means multi-core with CCU based coherence). I did not have enough time to try. You may want to check it out.
The branches are:

• rt/astral-v0
• culsans/dual-core
• astral-culsans-complete
  and other similar branches. I am not sure which one is the most stable one.

Irrelevant but if you just want dual core CVA6 with Coherence, try out https://github.com/pulp-platform/culsans .
Works like a charm for me.

[paulsc96]

Currently, you can instantiate multiple cores in Cheshire without hardware coherency, but the baremetal software setup for this is still in the works (#169). That said, you can just roll your own; this shouldn't be very difficult if you don't need to support all existing usecases of Cheshire.

You can, in principle, boot Linux without coherency by relying on self-invalidation consistency, but the required CVA6 parameterization and SDK are not the default ones and not maintained here (this is not my work or expertise).

Alternatively, you can wait for the work on Culsans (above) to be merged into Cheshire, which is planned in the future.

I'm keeping this open, but will consider it closed as completed when #169 is.

[bantierr]

Thank you so much for the answer @paulsc96 this is super helpful.
And also, thank you so much @anythingtemp8, i will try out culsans !