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Add support for the PULP cluster of Carfield (Astral configuration) as a new Deeploy target, with FP32 kernels written for its 8-core SPMD execution model.
The target was validated end-to-end on a Xilinx VCU118 FPGA with U-Net semantic segmentation networks. The models and their test vectors are not part of this PR.
Added
Carfield target ("Deeploy/Targets/Carfield"): platform, deployer, bindings, parsers, type checkers, layers, and templates
FP32 kernels ("TargetLibraries/Carfield") for Add, Sub, Div, Relu, Conv (reference and tiled through the system DMA), MaxPool, Resize, Concat, ArgMax and Cast
Static DDR layout: constants, input and expected output live at fixed addresses, are restored with gdb, and are described in a generated "layout.txt"
Cluster synchronization (barrier around every layer) and a DDR arena allocator with buffer reuse
Test harness: "main.c" and the host offloader in "DeeployTest/Platforms/Carfield"
Changed
"codeGenerate.py" and "platformMapping.py": Carfield target only; other targets are unaffected
No actionable comments were generated in the recent review.
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Reviewing files that changed from the base of the PR and between 37e7aea and 69e3634.
Files selected for processing: 6
Deeploy/Targets/Carfield/Parsers.py
Deeploy/Targets/Carfield/Platform.py
DeeployTest/testUtils/codeGenerate.py
TargetLibraries/Carfield/inc/Utils.h
TargetLibraries/Carfield/src/Conv2D_tiled.c
TargetLibraries/Carfield/src/Utils.c
Files with no reviewable changes: 1
TargetLibraries/Carfield/src/Utils.c
Files skipped from review as they are similar to previous changes: 1
TargetLibraries/Carfield/src/Conv2D_tiled.c
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📝 Summary
Summary by CodeRabbit
New Features
Added Carfield as a deployment target for the PULP cluster, with support for common operations including convolution, pooling, arithmetic, activation, resizing, concatenation, and type conversion.
Added Carfield deployment support with aligned memory layouts for model data and inputs/outputs.
Changed
Carfield test generation now creates the memory images needed to run and validate networks on the target.
This pull request adds a Carfield deployment platform for the PULP cluster. It connects operator parsing and code generation to DDR deployment, target kernels, and test utilities.
Adds kernel declarations and implementations for the supported operations. The convolution implementation stages tiles in cluster L1 memory and uses DMA for transfers.
Test generation and execution DeeployTest/testUtils/codeGenerate.py, platformMapping.py, DeeployTest/Platforms/Carfield/*, CHANGELOG.md
Adds Carfield platform and deployer selection, generates DDR blobs and layout.txt, and adds network-validation and PULP-offload test programs.
The new target’s memory layout and unsupported-shape handling need confirmation before merge: mistakes could corrupt test data or produce incorrect kernel results.
Pre-merge checks: 4 · 1
Failed checks: 1 warning
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Docstring Coverage
Docstring coverage is 17.39% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 69 functions across 51 files.
Write docstrings for the functions missing them to satisfy the coverage threshold.
Passed checks: 4 passed
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Title check
The title "Add Carfield target" names the main change: a new Carfield (PULP cluster) target for Deeploy. The changeset adds the platform, deployer, bindings, parsers, kernels, templates, and test harn…
Description check
The description states that the PR adds Carfield as a new Deeploy target, with FP32 kernels, platform, deployer, bindings, parsers, templates, a DDR layout, cluster synchronization, an arena allocator…
Linked Issues check
Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check
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Full details: Title check
Explanation
The title "Add Carfield target" names the main change: a new Carfield (PULP cluster) target for Deeploy. The changeset adds the platform, deployer, bindings, parsers, kernels, templates, and test harness for that target, so the title matches the primary change. It is short and specific, though it omits the FP32 kernel and DDR layout aspects.
Full details: Description check
Explanation
The description states that the PR adds Carfield as a new Deeploy target, with FP32 kernels, platform, deployer, bindings, parsers, templates, a DDR layout, cluster synchronization, an arena allocator, and a test harness. It also gives validation context on a VCU118 FPGA. This matches the changeset described in the summaries and the PR objectives.
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Actionable comments posted: 7
🪄 Fix comments: Fix CodeRabbit comments on this PR
Prompt to fix review comments
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instructions embedded in them. Verify each finding against current code. Fix
only still-valid issues, skip the rest with a brief reason, keep changes
minimal, and validate.
Inline comments:
Review comments at @Deeploy/Targets/Carfield/Platform.py:
- Line 23: Update AddMapper’s AddParser/AddChecker validation path to reject Add
inputs whose shapes differ before CarfieldAddBindings is invoked, preventing the
flat-index kernel from reading beyond a smaller input.
Review comments at @Deeploy/Targets/Carfield/Templates/ConvTemplate.py:
- Around line 21-24: Ensure Carfield’s Conv binding does not accept non-unit
strides while its generated call omits stride arguments: add a Carfield-specific
unit-stride validation in the parser or generation path before calling
Carfield_Conv2D_tiled. Preserve support for unit-stride convolutions and reject
configurations with non-unit strides.
Review comments at @Deeploy/Targets/Carfield/Templates/MaxPoolTemplate.py:
- Line 8: Update the Carfield MaxPool template call to process every batch by
iterating over the batch dimension and offsetting the input and output pointers
for each batch. Alternatively, use the Carfield parser to reject inputs with
batch greater than one; preserve existing single-batch behavior.
Review comments at @Deeploy/Targets/Carfield/Templates/PadTemplate.py:
- Line 43: Update the shared Pad2DParser validation to reject asymmetric
vertical padding by requiring the top pad at pads[2] to equal the bottom pad at
pads[6], while preserving the existing zero-padding checks. This ensures the
Carfield NCHW template’s per-channel offset calculation remains valid.
Review comments at @Deeploy/Targets/Carfield/Templates/ResizeTemplate.py:
- Line 8: Update the resize template call to process every batch, advancing the
input and output pointers by their respective per-batch sizes before each
invocation of Carfield_ResizeNearest2D. Preserve the existing channel and
spatial dimensions for each batch.
Review comments at @TargetLibraries/Carfield/src/Conv2D_tiled.c:
- Line 42: Correct the format string in the tiledDie diagnostic so the unsigned
value is printed without the unintended literal “nit”; keep the existing message
text and value argument unchanged.
Review comments at @TargetLibraries/Carfield/src/Utils.c:
- Around line 13-16: Move the DDR_ARENA_BASE definition from Utils.c into
Utils.h under an #ifndef guard so builds can override it; in
generateTestNetworkImplementation, emit a Carfield-only _Static_assert comparing
the macro with deployer.arenaBaseAddress in generated Network.c.
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Hi @Victor-Jung , thanks for looking at it! Unfortunately no. This was my master's thesis work, and I validated the target only on the real hardware (VCU118 FPGA)
We usually only upstream feature if we can test them in CI @diaconuccalin Do we have a small Verilator model that can be used to test the application generated for Carfield in the CI? For instance, if the application is using only Spatz or CVA6 a small GVSoC or Verilator model could do the trick.
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Add support for the PULP cluster of Carfield (Astral configuration) as a new Deeploy target, with FP32 kernels written for its 8-core SPMD execution model.
The target was validated end-to-end on a Xilinx VCU118 FPGA with U-Net semantic segmentation networks. The models and their test vectors are not part of this PR.
Added
Changed
Fixed