fix: guest-page-fault reporting for non-leaf VS-stage PTEs

[Maanvi212006]

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Why is this PR needed?

During two-stage address translation, a VS-stage page table entry (PTE) produces a guest physical address (GPA), which is then translated by the G-stage. According to the RISC-V Privileged Specification, for Sv39x4, if the generated GPA has non-zero bits in the range 63:41, the processor must raise a guest-page-fault.

The current implementation correctly handles this case for leaf VS-stage PTEs by setting ptw_stage_d to G_FINAL_STAGE. However, the non-leaf VS-stage PTE path leaves ptw_stage_d unchanged (S_STAGE), causing the exception to be reported as a normal page fault instead of a guest-page-fault.

This PR updates the non-leaf PTE path to use G_FINAL_STAGE, making its behavior consistent with the leaf PTE path and compliant with the RISC-V Privileged Specification.

Related Issue

Fixes #3401

Changes

• Update the non-leaf VS-stage PTE error path in core/cva6_mmu/cva6_ptw.sv.
• Replace:

  ptw_stage_d = ptw_stage_q;