The purpose of this project is to develop an FPGA synthesizable program capable of simulating ropes movement via verlet integration. The stack of the project is as follows:
- Hardware: FPGA
- Simulation: Verilator
- HDL: Verilog
The ADM and FSM diagarm are the main resources and idea for the implementation of the project. You can find them in the docs folder.
- Rope connected to a fixed point
- Rope enters the tension state
- Rope enters the whipcrack state
