[fpga] Fix ROM corruption on async reset assertion#649
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The async Mocha reset assertion can cause timing violations for BRAM control/address input signals, and corrupt the content of the ROM. This bug does not affect the ASIC implementation. This commit ensures both assertion and deassertion of the Mocha top reset on FPGA are synchronous to the clock, which prevents the issue.
marnovandermaas
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Great find! I was wondering about one alteration.
marnovandermaas
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Jul 8, 2026
marnovandermaas
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This change looks good to me. I re-ran the CI three times to make sure the FPGA test runs reliably now, and it does. So I think this is good to merge.
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The asynchronous Mocha reset assertion on FPGA can cause timing violations for BRAM control/address input signals, and corrupt the content of the ROM.
This PR adds a synchroniser to ensure both assertion and deassertion of the Mocha top reset on FPGA are synchronous to the clock, which prevents this issue.
Closes #639.