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Mpaci/cv32e40p testbench. CV32E40P core model. - #104
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The CV32E40P needs the CORE-V (Xpulp v2) instructions with the results of its RTL, which differ in places from the gvsoc-core handlers. For example, cv.macuRN wraps the accumulation at 32 bits before the shift, where lib_MAC_*_NR_R keeps the carry. The new subset reuses the gvsoc-core handlers and overrides the ones that differ. The priv handlers make a CSR access outside the map illegal, and ebreak follows dcsr.ebreakm and debug mode. cv.elw is a plain load, and its replay after an interrupt is not modelled. Assisted-by: Claude Signed-off-by: Marco Paci <marco.paci@chips.it>
The generic iss_v2 slots do not behave like the CV32E40P: they accept CSRs that the RTL does not implement, clear mcause on mret and take the mtvec base at boot from the boot address. The CV32E40P classes replace the CSR map, the HPM counters, the interrupt and debug controller, the exceptions and the hardware loops with the RTL behaviour. For example, mtvec at boot now comes from the mtvec_addr_i pin, and a debug entry takes the trigger, ebreak and halt request causes in the RTL order. Assisted-by: Claude Signed-off-by: Marco Paci <marco.paci@chips.it>
A checker that runs the model in lock-step with the RTL needs one record per executed instruction, and the model must take interrupts and debug entries at the same points as the RTL. cosim.hpp defines a versioned ABI of plain structs and pure virtual methods. The checker reports the pins, their samples and the decision points of the controller, and gives the data of the loads from testbench peripherals. Cv32e40pCosimModel builds the records from hooks in the slots, and does nothing until a checker calls configure(). Assisted-by: Claude Signed-off-by: Marco Paci <marco.paci@chips.it>
Cv32e40pConfig names the RTL parameters (FPU, ZFINX, COREV_PULP, COREV_CLUSTER, NUM_MHPMCOUNTERS), and one recipe builds the core for each of them, with the parameters in the ISA cache key. It relaxes the fence encodings as the RTL decoder does, drops the FP loads, stores and moves with ZFINX, and enables coherent fetch, since without an instruction cache code written by a store runs without fence.i. It needs the iss_v2 fixes proposed to gvsoc-core with this core (FP flags, RVC decoder, prefetch flush, misaligned split, opcode length). Assisted-by: Claude Signed-off-by: Marco Paci <marco.paci@chips.it>
The programs of the core-v-verif CV32E40P UVM testbench expect its memory map and its virtual peripherals: they print through 0x10000000 and report their end at 0x20000000. The cv32e40p_testbench target has 4 MB at 0 with boot address 0x80, the debug memory at 0x1A110800, and elsewhere a memory that reads 0 until written, with the peripherals. The first status, exit or signature write ends the run, unless stop_on_exit is false for co-simulation. The RTL parameters are SoC fields, and mtvec_addr drives the mtvec_addr_i input of the core. Assisted-by: Claude Signed-off-by: Marco Paci <marco.paci@chips.it>
Add nine programs of the core-v-verif CV32E40P testbench, built for six of its RTL configurations, and run them on four configurations of the cv32e40p_testbench target. The README gives the toolchain and the core-v-verif commit they were built from. The same binaries pass in the UVM testbench, where every instruction is compared with this model. Assisted-by: Claude Signed-off-by: Marco Paci <marco.paci@chips.it>
Marco Paci maintains the CV32E40P component: the core under cpu/iss_v2/*/cores/cv32e40p, the core recipe and the testbench under pulp/cv32e40p, and the examples. Assisted-by: Claude Signed-off-by: Marco Paci <marco.paci@chips.it>
This was referenced Oct 6, 2026
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I'm closing the other PR that were touching gvsoc/gvsoc-core and added the CV32E40P core to gvsoc-pulp, with a cv32e40p_testbench target and a co-simulation interface (
cosim.hpp). This interface is used to facilitate controlling the GVSOC model execution step-by-step during the RTL simulation.As a note to leave here this model is used as the reference model of the core-v-verif CV32E40P testbench through https://github.com/marpac3/gvsoc_rvvi.
I have moved everything in gvsoc-pulp, in new folders and files and added myself as code owner of those files.
It replaces gvsoc/gvsoc-core#146 and #74, which I am closing.
There are also a few example to run test on the model.