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Rounding mode 4 (round to nearest, ties to max magnitude) used to abort the simulation because fenv has no such mode. flexfloat_sanitize already resolves rounding in software from the round and sticky bits, so RMM only needs a flag: with FE_TONEAREST set and flexfloat_rmm active, a tie rounds away from zero instead of to even. The flag is scoped to the per-instruction set/restore pair in setFFRoundingMode. Overflow now honours the direction of the rounding mode as IEEE 754 requires: toward-zero (always), downward (positive results) and upward (negative results) clamp to the largest finite value instead of returning infinity. (cherry picked from commit aaedd2d)
The RMM path of the flexfloat float-to-int conversions negated the input to round on its magnitude, then dropped the sign: - lib_flexfloat_cvt_wu_ff_round returned |x| for a negative x instead of 0. Unsigned conversion of a negative value saturates to 0; the negation hid the sign from double_to_uint, which already saturates correctly, so the magnitude leaked through (0xffffffff / |x| instead of 0). - lib_flexfloat_cvt_w_ff_round saturated a negative overflow to INT32_MIN+1 (0x80000001) instead of INT32_MIN (0x80000000): |INT32_MIN| = 2^31 is not representable as a positive int32, so the magnitude saturated to INT32_MAX and negating it was off by one. Fix: do not hide the sign from double_to_uint/double_to_int, which saturate with the correct signed/unsigned bounds; restore the saved rounding mode (was passing new_round instead of old, unlike the unsigned sibling). Validated bit-exact against the CV32E40P FPnew conversions (F and Zfinx configurations) on directed boundary vectors. (cherry picked from commit 8aab68b)
This was referenced Aug 21, 2026
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Problem. Three IEEE-754 conformance gaps in the shared flexfloat FP
backend:
simulation: host
fenvhas no such mode.requires a clamp to the largest finite value: toward-zero always, downward
for positive results, upward for negative results.
fcvt.wu.s/fcvt.w.son the RMM path dropped the sign of the input:converting a negative value to unsigned returned |x| instead of saturating
to 0, and signed negative overflow saturated to INT32_MIN+1 instead of
INT32_MIN. One path also failed to restore the saved rounding mode.
Fix. RMM becomes a scoped flag resolved in software by
flexfloat_sanitize, which already re-rounds from the round/sticky bits (atie rounds away from zero under FE_TONEAREST). Overflow honours the rounding
direction. The conversions pass the signed value to
double_to_uint/double_to_int, which saturate with the correct bounds.Validation. Lockstep RVVI co-simulation of the GVSOC ISS against the
CV32E40P RTL (F and Zfinx configurations), with corev-dv random tests and
directed FP tests; bit-exact against the CV32E40P FPnew conversions on
directed boundary vectors.
pulp-openandsnitchbuild clean and givebit-identical instruction traces on an FP workload before/after.
The second commit preserves its original author (@nikgiu).