feat(cv32e40p): add CV32E40P ISS core model

models/cpu/iss/flexfloat/flexfloat.h

@@ -195,6 +195,11 @@ uint_t flexfloat_denorm_frac(const flexfloat_t *a, int_fast16_t exp);
 uint_t flexfloat_pack(flexfloat_desc_t desc, bool sign, int_fast16_t exp, uint_t frac);
 void flexfloat_sanitize(flexfloat_t *a);
 
+// Round-to-nearest, ties away from zero (RISC-V RMM). The C fenv has no such
+// mode: callers set FE_TONEAREST plus this flag, and flexfloat_sanitize then
+// resolves ties away from zero instead of to even.
+extern int flexfloat_rmm;
+
 
 // Bit-level access
 

models/cpu/iss/include/core.hpp

@@ -32,6 +32,9 @@ class Core
 {
 public:
     Core(Iss &iss);
+#ifdef CONFIG_GVSOC_ISS_CV32E40P
+    virtual ~Core() = default;
+#endif
 
     void build();
     void reset(bool active);
@@ -40,6 +43,14 @@ class Core
     iss_reg_t dret_handle();
     iss_reg_t sret_handle();
     int mode_get() { return this->mode; }
+#ifdef CONFIG_GVSOC_ISS_CV32E40P
+    /* Privilege-mode restore on MRET. Default: from mstatus.mpp. */
+    virtual void mret_mode_restore();
+
+    /* mstatus_write_mask customization, called at end of build() after the
+     * generic mask is computed. Default: no-op. */
+    virtual void mstatus_write_mask_fixup() {}
+#endif
     void mode_set(int mode);
     iss_reg_t load_reserve_addr_get() { return this->load_reserve_addr; }
     void load_reserve_addr_set(iss_reg_t addr) { this->load_reserve_addr = addr; }
@@ -50,15 +61,24 @@ class Core
     vp::Trace event_jal;
     vp::Trace event_jalr;
 
+#ifdef CONFIG_GVSOC_ISS_CV32E40P
+protected:
+    Iss &iss;
+    iss_reg_t mstatus_write_mask;
+#endif
 private:
     bool mstatus_update(bool is_write, iss_reg_t &value);
     bool sstatus_update(bool is_write, iss_reg_t &value);
 
+#ifndef CONFIG_GVSOC_ISS_CV32E40P
     Iss &iss;
+#endif
     vp::Trace trace;
 
     int mode;
+#ifndef CONFIG_GVSOC_ISS_CV32E40P
     iss_reg_t mstatus_write_mask;
+#endif
     iss_reg_t sstatus_write_mask;
     iss_reg_t load_reserve_addr;
     bool reset_stall = false;

models/cpu/iss/include/cores/cv32e40p/class.hpp

@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2020 GreenWaves Technologies, SAS, ETH Zurich and
+ *                    University of Bologna
+ * Copyright (C) 2026 Fondazione Chips-it
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Authors: Marco Paci, Fondazione Chips-it (marco.paci@chips.it)
+ */
+
+
+#pragma once
+
+
+#include <vp/vp.hpp>
+#include <vp/register.hpp>
+#include <cpu/iss/include/lsu.hpp>
+#include <cpu/iss/include/decode.hpp>
+#include <cpu/iss/include/trace.hpp>
+#include <cpu/iss/include/cores/cv32e40p/csr.hpp>
+#include <cpu/iss/include/dbgunit.hpp>
+#include <cpu/iss/include/cores/cv32e40p/exception.hpp>
+#include <cpu/iss/include/syscalls.hpp>
+#include <cpu/iss/include/timing.hpp>
+#include <cpu/iss/include/cores/cv32e40p/regfile.hpp>
+#ifdef CONFIG_GVSOC_ISS_RISCV_EXCEPTIONS
+#include <cpu/iss/include/cores/cv32e40p/irq.hpp>
+#else
+#include <cpu/iss/include/irq/irq_external.hpp>
+#endif
+#include <cpu/iss/include/cores/cv32e40p/core.hpp>
+#if defined(CONFIG_GVSOC_ISS_MMU)
+#include <cpu/iss/include/mmu.hpp>
+#endif
+#if defined(CONFIG_GVSOC_ISS_PMP)
+#include <cpu/iss/include/pmp.hpp>
+#endif
+#include <cpu/iss/include/memcheck.hpp>
+#include <cpu/iss/include/insn_cache.hpp>
+#include <cpu/iss/include/exec/exec_inorder.hpp>
+#include <cpu/iss/include/prefetch/prefetch_single_line.hpp>
+#include <cpu/iss/include/gdbserver.hpp>
+
+class IssWrapper;
+
+
+class Iss
+{
+public:
+    Iss(IssWrapper &top);
+
+    Cv32e40pRegfile regfile;
+    Exec exec;
+    InsnCache insn_cache;
+    Timing timing;
+    Cv32e40pCore core;
+    Prefetcher prefetcher;
+    Decode decode;
+    Cv32e40pIrq irq;
+    Gdbserver gdbserver;
+    Lsu lsu;
+    DbgUnit dbgunit;
+    Syscalls syscalls;
+    Trace trace;
+    Cv32e40pCsr csr;
+#if defined(CONFIG_GVSOC_ISS_MMU)
+    Mmu mmu;
+#endif
+#if defined(CONFIG_GVSOC_ISS_PMP)
+    Pmp pmp;
+#endif
+    Cv32e40pException exception;
+    Memcheck memcheck;
+
+    vp::Component &top;
+};
+
+class IssWrapper : public vp::Component
+{
+
+public:
+    IssWrapper(vp::ComponentConf &config);
+
+    void start();
+    void stop();
+    void reset(bool active);
+
+    Iss iss;
+
+private:
+    vp::Trace trace;
+};
+
+inline Iss::Iss(IssWrapper &top)
+    : prefetcher(*this), exec(top, *this), insn_cache(*this), decode(*this), timing(*this), core(*this), irq(*this),
+      gdbserver(*this), lsu(top, *this), dbgunit(*this), syscalls(top, *this), trace(*this), csr(*this),
+      regfile(top, *this), exception(*this), memcheck(top, *this), top(top)
+#if defined(CONFIG_GVSOC_ISS_MMU)
+    , mmu(*this)
+#endif
+#if defined(CONFIG_GVSOC_ISS_PMP)
+    , pmp(*this)
+#endif
+{
+}
+
+#include "cpu/iss/include/isa/rv64i.hpp"
+#include "cpu/iss/include/isa/rv32i.hpp"
+#include "cpu/iss/include/isa/rv32c.hpp"
+#include "cpu/iss/include/isa/zcmp.hpp"
+#include "cpu/iss/include/isa/rv32a.hpp"
+#include "cpu/iss/include/isa/rv64c.hpp"
+#include "cpu/iss/include/isa/rv32m.hpp"
+#include "cpu/iss/include/isa/rv64m.hpp"
+#include "cpu/iss/include/isa/rv64a.hpp"
+#include "cpu/iss/include/isa/rvf.hpp"
+#include "cpu/iss/include/isa/rvd.hpp"
+#include "cpu/iss/include/cores/cv32e40p/priv.hpp"
+#include <cpu/iss/include/isa/corev.hpp>
+
+
+#include <cpu/iss/include/exec/exec_inorder_implem.hpp>

models/cpu/iss/include/cores/cv32e40p/core.hpp

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2020 GreenWaves Technologies, SAS, ETH Zurich and
+ *                    University of Bologna
+ * Copyright (C) 2026 Fondazione Chips-it
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Authors: Marco Paci, Fondazione Chips-it (marco.paci@chips.it)
+ */
+
+#pragma once
+
+#include <cpu/iss/include/core.hpp>
+
+class Cv32e40pCore : public Core
+{
+public:
+    Cv32e40pCore(Iss &iss) : Core(iss) {}
+
+protected:
+    /* CV32E40P is M-mode only.
+     * CSR writes can set MPP to 0, but
+     * MRET must ignore that and stay in M-mode. */
+    void mret_mode_restore() override;
+
+    /* CV32E40P mstatus_write_mask FPU-aware.
+     * only MIE(3) + MPIE(7) writable; MPP forced to M by hardware.
+     * With FPU: add FS(14:13). */
+    void mstatus_write_mask_fixup() override;
+};

models/cpu/iss/include/cores/cv32e40p/csr.hpp

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2020 GreenWaves Technologies, SAS, ETH Zurich and
+ *                    University of Bologna
+ * Copyright (C) 2026 Fondazione Chips-it
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Authors: Marco Paci, Fondazione Chips-it (marco.paci@chips.it)
+ */
+
+#pragma once
+
+#include <cpu/iss/include/csr.hpp>
+
+class Cv32e40pCsr : public Csr
+{
+public:
+    Cv32e40pCsr(Iss &iss);
+
+    void build();           // Calls Csr::build() then build_cv32e40p()
+    void build_cv32e40p();  // CV32E40P-specific CSR customization
+    void reset(bool active);
+
+    bool mstatus_access(bool is_write, iss_reg_t &value) override;
+    bool mcycle_access(bool is_write, iss_reg_t &value) override;
+    void mstatus_read_fixup(iss_reg_t &value) override;
+
+    // FP/Vector CSR access pre-check.
+    // Returns true (illegal) when mstatus[FS] == 00 (Off)
+    // raises illegal-instruction on FP CSR access while FS=Off.
+    bool fp_access_illegal() override;
+
+    // Promote mstatus.FS to Dirty(11) on any FP state change.
+    // RTL (cv32e40p_cs_registers.sv) forces FS=Dirty when FPU=1 && ZFINX=0 on
+    // FP regfile write, fflags update, or FP-CSR write. SD(bit31) is derived
+    // on read (SD = FS==3), not stored here.
+    void fp_state_dirty() override;
+
+    // CoreV2 HWLOOP CSR mapping.
+    //   0xCC0..0xCC2 → 0..2  (lpstart0/lpend0/lpcount0)
+    //   0xCC4..0xCC6 → 4..6  (lpstart1/lpend1/lpcount1)
+    //   gap at 0xCC3 / outside range → -1.
+    int hwloop_csr_index(iss_reg_t reg) override;
+
+    // CoreV2 HWLOOP CSR names for trace messages.
+    const char *custom_csr_name(iss_reg_t reg) override;
+
+    // EBREAK in M-mode enters debug when dcsr.ebreakm=1.
+    // RISC-V Debug Spec: bit 15 of dcsr is ebreakm.
+    bool ebreak_m_mode_enters_debug() override;
+
+    // PULP custom CSRs (0xCD0-0xCD2)
+    CsrReg uhartid;     // 0xCD0 — duplicate of mhartid (user-mode readable)
+    CsrReg privlv;      // 0xCD1 — current privilege level
+    CsrReg zfinx_csr;   // 0xCD2 — ZFINX indicator; undeclared (illegal) when FPU=1 && ZFINX=0
+
+private:
+    int64_t mcycle_offset = 0;
+    bool m_fpu_in_isa = false;
+    bool m_zfinx = false;
+};

models/cpu/iss/include/cores/cv32e40p/exception.hpp

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2020 GreenWaves Technologies, SAS, ETH Zurich and
+ *                    University of Bologna
+ * Copyright (C) 2026 Fondazione Chips-it
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Authors: Marco Paci, Fondazione Chips-it (marco.paci@chips.it)
+ */
+
+#pragma once
+
+#include <cpu/iss/include/exception.hpp>
+
+class Cv32e40pException : public Exception
+{
+public:
+    /* CV32E40P always aligns the trap vector to 4 bytes
+    set base-class alignment mask accordingly. */
+    Cv32e40pException(Iss &iss) : Exception(iss)
+    {
+        this->trap_vector_align_mask = ~(iss_reg_t)0x3;
+    }
+};

models/cpu/iss/include/cores/cv32e40p/irq.hpp

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2020 GreenWaves Technologies, SAS, ETH Zurich and
+ *                    University of Bologna
+ * Copyright (C) 2026 Fondazione Chips-it
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Authors: Marco Paci, Fondazione Chips-it (marco.paci@chips.it)
+ */
+
+#pragma once
+
+#include <cpu/iss/include/irq/irq_riscv.hpp>
+
+class Cv32e40pIrq : public Irq
+{
+public:
+    Cv32e40pIrq(Iss &iss) : Irq(iss) {}
+
+    bool mip_access(bool is_write, iss_reg_t &value) override;
+    bool mie_access(bool is_write, iss_reg_t &value) override;
+    bool mtvec_access(bool is_write, iss_reg_t &value) override;
+    void elw_irq_unstall() override;
+    iss_reg_t compute_trap_entry(iss_reg_t base, int cause, bool is_interrupt) override;
+
+protected:
+    void register_csr_callbacks() override;
+};