ECE 2300 Digital Logic and Computer Organization
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ece2300-tut02-git
ece2300-tut02-git PublicECE 2300 Tutorial 2: Git Distributed Version Control System
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github-actions-prebuild
github-actions-prebuild PublicGitHub repo with prebuilt iverilog and verilator binaries
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ece2300-sec02-verilog-gl
ece2300-sec02-verilog-gl PublicECE 2300 Section 2: Verilog Combinational Gate-Level Design
Verilog 140
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ece2300-sec03-verilog-testing
ece2300-sec03-verilog-testing PublicECE 2300 Section 3: Verilog Testing
Python 4
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ece2300-sec04-lab2-head-start
ece2300-sec04-lab2-head-start PublicECE 2300 Section 4: Lab 2 Head Start
Python 3
Repositories
- ece2300-verible Public Forked from chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
- pyverilog Public Forked from PyHDI/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
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