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1. wide_alu_ip wide_alu_ip Public

   Fullstack AXI ip integration from pulp training

   SystemVerilog 4

2. axi_node axi_node Public

   Forked from pulp-platform/axi_node

   AXI X-Bar

   SystemVerilog

3. fpnew fpnew Public

   Forked from openhwfoundation/cvfpu

   Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

   SystemVerilog

4. mchan mchan Public

   Forked from pulp-platform/mchan

   SystemVerilog

5. regression_tests regression_tests Public

   Forked from pulp-platform/regression_tests

   Adding iDMA tests

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6. pulp_cluster pulp_cluster Public

   Forked from pulp-platform/pulp_cluster

   The multi-core cluster of a PULP system.

   SystemVerilog