05 branch instructions - #30
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…nce item - Define ALUOp ChiselEnum with 11 operations (ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU, PASSB) - Implement 32-bit combinational ALU in ALU.scala following RV32I spec - Write comprehensive TDD testbench with one test class per operation and edge cases - Complete alu_seq_item.sv with randomized fields, UVM factory registration, and aluOp_constraint
Implement Assignment 02: ALU with full Chisel testbench and UVM seque…
- Implement all pipeline stages: IF, ID, EX, MEM, WB - Implement all pipeline barriers: IFBarrier, IDBarrier, EXBarrier, MEMBarrier, WBBarrier - Implement dual-read single-write register file (x0 hardwired to zero) - Define uopc ChiselEnum for all R-type and I-type micro-operations - Port ALU from Assignment02 into the pipeline project - Wire all stages and register file in PipelinedRV32Icore - Extend test program with I-type instructions and corner cases: ANDI, ORI, XORI, SLTI, SLTIU, SLLI, SRLI, SRAI SLT vs SLTU with negative value showing signed/unsigned divergence
Added complete forwarding unit implementation that resolves RAW (Read-After-Write) data hazards in the 5-stage pipeline without stalls: - Forwarding Unit: Detects hazards by comparing source registers (rs1, rs2) in EX stage with destination registers in MEM and WB stages - Enhanced Pipeline Barriers: Added write enable signals and register address tracking through barriers - EX Stage: Implements forwarding muxes with priority: MEM > WB > ID - Register File: Write-through forwarding for simultaneous read/write on same register - Comprehensive Test Suite: 10 test cases covering all forwarding scenarios: 1. RAW hazards from MEM stage 2. RAW hazards from WB stage 3. Both operands from same register 4. Dependency chains 5. Mixed source forwarding 6. Logical operations (AND, OR, XOR) 7. Shift operations (SLL, SRL) 8. Comparison operations (SLT) 9. No hazard baseline 10. Multiple independent chains All 10 tests passing - 100% success rate Verilog RTL generated successfully
Add complete support for B-type and J-type instructions to the 5-stage pipelined RISC-V processor: Instruction Set: - Branch instructions: BEQ, BNE, BLT, BGE, BLTU, BGEU - Jump instructions: JAL, JALR Features: - Instruction decoding for all B-type and J-type formats - Branch condition evaluation with operand forwarding - Branch target and return address calculation - Simple static branch prediction (not-taken for conditional, always-taken for unconditional) - Pipeline flushing mechanism for control hazard handling - Extended data hazard forwarding for branch operands Pipeline Modifications: - IF stage: Added branch target and flush inputs - ID stage: Added B-type and J-type instruction decoding - EX stage: Added branch condition evaluation and target calculation - All barriers: Added control signal propagation - Core: Added pipeline control wiring for flush and branch target Testing: - All 19 original test cases from Assignment 4 pass - Backward compatible with existing R-type and I-type instructions - Branch prediction and pipeline flushing verified
Replace flush-propagation-through-barriers approach with kill-bit propagation: - IFBarrier/IDBarrier tag wrong-path instructions with kill bit on flush - EXBarrier/MEMBarrier propagate kill bit and suppress writeEn at WB stage - WBstage gates register writes via writeEn from MEMBarrier - Add 4 passing control hazard tests (BEQ/BNE not-taken, BLT/BGE taken)
Replace kill-bit propagation with NOP injection approach: - IFBarrier: inserts NOP (addi x0,x0,0) on flush to squash WP2 - IDBarrier: zeroes all registers on flush to squash WP1 - wr_en computed in ID stage and propagated through EX/MEM barriers - EXBarrier/MEMBarrier: simple passthroughs with outWriteEn = wr_en && !xcpt - WBBarrier: simplified to checkRes + xcptInvalid only - All 5 tests pass
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