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1. Basys3-7-Segment-Display-Counter Basys3-7-Segment-Display-Counter Public

   VHDL design for the Digilent Basys3 (Xilinx Artix-7) FPGA board that drives the on-board 4-digit 7-segment display. After reset it steps through the display's digit positions, then cycles through t…

   VHDL 1

2. ESP32-4DOF-Robotic-Arm ESP32-4DOF-Robotic-Arm Public

   -DOF Robotic Arm using ESP32, Potentiometers, and SG90 Servos with Teach-and-Repeat Functionality

   C++

3. 64bit-cpu-basys3 64bit-cpu-basys3 Public

   Custom 64-bit CPU/SoC in Verilog — integer ALU, floating-point unit, register file, program counter — targeting the Digilent Basys3 (Artix-7) FPGA in Vivado.

   Verilog

4. Arria10-ram_ip-io-test Arria10-ram_ip-io-test Public

   Quartus/SignalTap test for the Intel Arria 10 SoC Dev Kit — exercises a 1024×256 single-port RAM IP through a write/read/done sequence with basic board I/O.

   VHDL