Describe the bug
In the SMP configuration (configNUMBER_OF_CORES > 1), tasks.c:510 declares:
PRIVILEGED_DATA STATIC volatile BaseType_t xYieldPendings[ configNUMBER_OF_CORES ] = { pdFALSE };The array has configNUMBER_OF_CORES elements, but the initializer list has a single
element, so the remaining elements are only implicitly zero-initialized. This is a violation of MISRA C:2012 Rule 9.3 (Required): "Arrays shall not be partially initialized".
PR #973 fixed the same pattern for the same rule in portable/Common/mpu_wrappers_v2.c (= { NULL } → = { 0 }). pdFALSE is ( ( BaseType_t ) 0 ) (include/projdefs.h:52), so this is the same class.
Expected behavior
No Rule 9.3 violation. Proposed change (no behavior change, keeps all cores
zero-initialized).
PRIVILEGED_DATA STATIC volatile BaseType_t xYieldPendings[ configNUMBER_OF_CORES ] = { 0 };
Alternatively, add a documented deviation in MISRA.md if the implicit zero-initialization is intentional and preferred as-is.
Describe the bug
In the SMP configuration (configNUMBER_OF_CORES > 1),
tasks.c:510declares:The array has
configNUMBER_OF_CORESelements, but the initializer list has a singleelement, so the remaining elements are only implicitly zero-initialized. This is a violation of MISRA C:2012 Rule 9.3 (Required): "Arrays shall not be partially initialized".
PR #973 fixed the same pattern for the same rule in portable/Common/mpu_wrappers_v2.c (= { NULL } → = { 0 }). pdFALSE is ( ( BaseType_t ) 0 ) (include/projdefs.h:52), so this is the same class.
Expected behavior
No Rule 9.3 violation. Proposed change (no behavior change, keeps all cores
zero-initialized).
Alternatively, add a documented deviation in MISRA.md if the implicit zero-initialization is intentional and preferred as-is.