hls_examples

FFT demo designs built on a shared Vitis HLS FFT core (hls/fft_wrapper). There are two board variants:

Variant	Board	Part	Flow
fft_demo_zybo	Digilent Zybo Z7-10	xc7z010clg400-1	Makefile-driven PACK/INTEG + Yocto (EDF) SD image
fft_project	TUL PYNQ-Z2	xc7z020clg400-1	Scripted Vivado project + PYNQ overlay

Prerequisites

• AMD Vivado / Vitis 2026.1 on PATH.
• git submodule update --init (pulls submodules/PYNQ, whose boards/ip is needed by the PYNQ-Z2 project).
• For the Zybo Yocto build: repo and the EDF/Yocto host tools (bitbake fetches the rest). The first build runs repo init && repo sync, which is large and one-time.

FFT HLS IP (shared by both flows)

make hls-fft_wrapper      # or: make build_hls  (builds every HLS project)

Produces hls/fft_wrapper/vitis_project/hls/impl/ip, consumed by both the Zybo and PYNQ-Z2 flows. The Zybo Makefile flow builds this automatically as a dependency; the PYNQ-Z2 flow expects it to already exist.

Zybo — fft_demo_zybo (Makefile flow)

Config: cfg/fft_demo_zybo.cfg.json; build scripts under scripts/. The full chain to a bootable SD image is a single target:

make gen-sdcard-image

This runs, in order: HLS export → Vivado PACK (package the cores) → INTEG (block design + export the XSA) → device tree (sdtgen) → Yocto machine config → boot.bin + wic rootfs → stage boot.bin and the notebooks into the image.

Useful individual stages:

Target	What it produces
make build_fft_fpga	XSA only (HLS → PACK → INTEG): target/fft_demo_zybo_integ/fft_demo_top_wrapper.xsa
make rtl_package	Vivado PACK stage (packaged cores)
make rtl_integ	Vivado INTEG stage (block design + XSA)
make build-bootbin	FSBL / boot.bin
make build-linux	Yocto wic disk image
make gen-sdcard-image	Final image with boot.bin + notebooks staged in

Build options (override on the command line):

• LINUX_EDF_PASSWORD=... — password for root and the amd-edf user (default test123).
• BOARD_HOSTNAME=... — target hostname (default amd-edf.local).

LINUX_EDF_PASSWORD=hunter2 make build-linux

Update a running board's boot.bin over the network (scp + reboot):

make load_boot.bin

Open the integration project in the Vivado GUI (after an INTEG run):

vivado target/fft_demo_zybo_integ/fft_demo_zybo_integ.xpr

PYNQ-Z2 — fft_project (Vivado script flow)

A scripted Vivado project under vivado/fft_project/, targeting the TUL PYNQ-Z2. Prerequisite: build the FFT HLS IP (above) and init submodules so the PYNQ boards/ip is present.

cd vivado/fft_project

# 1. Recreate the Vivado project (fft_project.xpr) from the checked-in script.
vivado -mode batch -source create_vivado_project.tcl

# 2. Implement to a bitstream and export the block-design tcl.
vivado -mode batch -source create_overlay_files.tcl

# 3. Copy the overlay (bit/hwh/tcl) + notebook to the board's SMB shares.
./copy_overlay_files.sh

Notes:

• create_vivado_project.tcl resolves source paths relative to origin_dir, which defaults to . — run it from vivado/fft_project/, or pass -tclargs --origin_dir <path>. Use -tclargs --project_name <name> to override the project name (default fft_project).
• Outputs: fft_project.runs/impl_1/fft_project_wrapper_wrapper.bit, fft_project.gen/sources_1/bd/fft_project_wrapper/hw_handoff/fft_project_wrapper.hwh, and fft_project_wrapper.tcl.
• copy_overlay_files.sh pushes those plus jupyter/fft_project.ipynb to the board over SMB. Edit OVERLAY_DEST / NOTEBOOK_DEST (the 192.168.2.99 share) near the top of the script for your board.
• Open the GUI (after step 1): vivado vivado/fft_project/fft_project.xpr.

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Appendix: Nix development environment

The repo ships a flake.nix that provides a reproducible dev shell with all the host tooling both flows need. Most importantly it is an FHS sandbox (buildFHSEnv): it recreates the conventional /usr/lib layout that AMD's Xilinx tools (Vivado, Vitis HLS, the Vitis IDE) expect but that NixOS does not provide natively, so those tools run unmodified.

Enter the shell from the repo root:

nix develop

(Requires flakes; if not enabled globally, prepend --experimental-features 'nix-command flakes'.) The shell is x86_64-linux only, since the Xilinx tools ship for that architecture.

What it provides:

• FHS sandbox with the X11 / GTK / font / audio libraries Vivado and the Vitis IDE need at runtime.
• Host toolchain pinned to GCC 14 — nixpkgs-unstable now ships GCC 15, whose C23 default breaks older poky (scarthgap) build-host helpers — plus binutils, verilator, and clang-tools (for make clang_format).
• Python environment rendered from requirements.txt (via pyproject-nix).
• Yocto / EDF host tools used by the Makefile stages: repo (source sync), openssl (hashes LINUX_EDF_PASSWORD), perl (OE rpm packaging), and the wic cp toolchain — e2fsprogs/debugfs (ext4 rootfs), mtools and dosfstools (vfat boot partition).
• BitBake env passthrough wired up so its stripped subprocess environment still lets the Nix GCC wrapper locate the glibc startup files during host-tool compilation.

Notes:

• The flake supplies the runtime environment, not the Xilinx tools themselves. Install AMD Vivado / Vitis 2026.1 separately and source its settings64.sh from inside the shell.
• On NixOS, run the Xilinx tools (and the Makefile flows that invoke them) from within nix develop — outside the FHS shell they will not find their dependencies.