VeriLens is an open-source hardware visualization tool that turns Verilog and SystemVerilog projects into interactive, explorable hardware diagrams.
Unlike simple static schematic generators, VeriLens is designed as a project-aware hardware comprehension tool. It analyzes an entire Verilog/SystemVerilog codebase, extracts structural hierarchy and connectivity, validates the design model, and renders zoomable diagrams that help users understand how modules, signals, and subsystems fit together.
The goal is not to replace a simulator, synthesizer, or full compiler. Instead, VeriLens focuses on making hardware projects easier to explore, debug, and explain through visualizations.
You may view more details on the website: VeriLens Website