I'm a Digital Design Engineer and PhD Candidate specializing in the high-performance implementation of digital systems. My core expertise is at the intersection of computer architecture and hardware design, focusing on creating efficient solutions for both ASIC and FPGA platforms.
| Domain | Description |
|---|---|
| VLSI & Hardware Design | End-to-end design, synthesis, and implementation for ASIC and FPGA using Verilog and VHDL. |
| Computer Arithmetic | Developing novel, resource-efficient circuits for fundamental operations, including custom multipliers and accumulation schemes. |
| SoC Design | Integrating and verifying complex intellectual property (IP) blocks within System-on-Chip (SoC) architectures. |
| Custom FPGA Fabrics | Researching and developing custom, application-specific FPGA fabric and routing architectures. |
| Category | Skills & Tools |
|---|---|
| Hardware Languages | Verilog, VHDL, SystemVerilog |
| Scripting & Automation | Python, Shell Scripting |
| Design Platforms | OpenFPGA, Commercial FPGA toolchains (e.g., Vivado), ASIC workflows, Git/GitHub, Linux |
A resource-efficient design approach for integer multipliers, optimizing for area and power by leveraging multi-cycle folding and the Karatsuba algorithm.
- Authors: A. Houraniah, H. F. Ugurdag and C. E. Dedeagac
- Journal/Conference: 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Kalamata, Greece
- DOI: 10.1109/ISVLSI65124.2025.11130295
- Keywords: Multi-cycle multiplier, folded multiplier, computer arithmetic, VLSI.
A highly-pipelined circuit designed to maximize the throughput of reduction/accumulation operations, tailored for efficient deployment on FPGAs.
- Authors: A. Houraniah, H. F. Ugurdag and F. Aydin
- Journal/Conference: IEEE Embedded Systems Letters
- DOI: 10.1109/LES.2025.3602852
- Keywords: Fully pipelined reduction circuits, floating-point accumulation, FPGA, computer arithmetic.
| Platform | Link |
|---|---|
| linkedin.com/in/houraniah/ | |
| ORCID | orcid.org/0000-0001-7925-8888 |
| houraniah@gmail.com |