Issues

• readOnly access (register and field level) blocks backdoor writes, contradicting documented behavior

  intel/rohd-hcl#297 · Filter by author caflore1 opened on Sep 2, 2026

• Add asyncReset support to CsrTopConfig

  intel/rohd-hcl#295 · Filter by author caflore1 opened on Aug 31, 2026

• CSRs create a lot of modules

  enhancement
  intel/rohd-hcl#291 · Filter by author desmonddak opened on Jun 8, 2026

• [Bug] Axi4MemorySubordinate: multi-beat write bursts store only the last beat's data at every address

  intel/rohd-hcl#290 · Filter by author caflore1 opened on Jun 5, 2026

• Options for persistence of memory in MemoryModel

  enhancement
  intel/rohd-hcl#276 · Filter by author mkorbel1 opened on Dec 31, 2025
  1

• Gracefully handle fewer than 2 requests to arbitrate between

  bug
  intel/rohd-hcl#272 · Filter by author mkorbel1 opened on Dec 5, 2025

• Wishbone Interconnect

  enhancement
  intel/rohd-hcl#269 · Filter by author RossComputerGuy opened on Nov 24, 2025
  1

• Update Fifo to leverage summation components

  enhancementgood first issue
  intel/rohd-hcl#267 · Filter by author mkorbel1 opened on Oct 31, 2025

• Expose nextCount in Counter

  enhancement
  intel/rohd-hcl#264 · Filter by author mkorbel1 opened on Oct 7, 2025

• Update ShiftRegister to carry a type through

  enhancement
  intel/rohd-hcl#257 · Filter by author mkorbel1 opened on Sep 11, 2025

• Update RegisterFile to use a LogicArray internally

  enhancement
  intel/rohd-hcl#256 · Filter by author mkorbel1 opened on Sep 11, 2025
  

• FP NaN are not comparable (e.g. nan != nan)

  bug
  intel/rohd-hcl#252 · Filter by author desmonddak opened on Sep 3, 2025

• FixedPoint and FixedPointValue have different default values for signed

  bug
  intel/rohd-hcl#249 · Filter by author desmonddak opened on Aug 22, 2025
  1

• FloatingPointConverter fails on narrowing mantissa with explicitJBit

  bug
  intel/rohd-hcl#241 · Filter by author desmonddak opened on Jul 17, 2025

• StaticOrRuntimeParameter does not check for name on Runtime Logic signal

  bug
  intel/rohd-hcl#235 · Filter by author desmonddak opened on Jul 14, 2025

• Shifting by constants produces complex names when using << versus >>>

  enhancement
  intel/rohd-hcl#234 · Filter by author desmonddak opened on Jul 12, 2025
  2

• Add support in CSR configuration for user-defined access types

  enhancement
  intel/rohd-hcl#228 · Filter by author mkorbel1 opened on Jul 9, 2025
  1

• Remove .sv file generation from tests, add check to prevent them in the future

  bug
  intel/rohd-hcl#221 · Filter by author mkorbel1 opened on Jul 1, 2025

• Upgrade flutter version by dropping use of dart:html in confapp

  enhancement
  intel/rohd-hcl#213 · Filter by author desmonddak opened on Jun 25, 2025

• FloatingPointValue unit of least precision (ulp) is incorrect for subnormals

  bug
  intel/rohd-hcl#206 · Filter by author desmonddak opened on May 28, 2025

• Make extension-generated modules nameable

  enhancement
  intel/rohd-hcl#201 · Filter by author mkorbel1 opened on May 20, 2025

• Add an easy way for arithmetic Values to convert to Const versions of corresponding signals

  enhancement
  intel/rohd-hcl#200 · Filter by author mkorbel1 opened on May 20, 2025

• Add basic operations directly on arithmetic types

  enhancement
  intel/rohd-hcl#199 · Filter by author mkorbel1 opened on May 20, 2025
  

• FloatingPointMultiplier to narrower FP type

  enhancement
  intel/rohd-hcl#194 · Filter by author desmonddak opened on Apr 22, 2025

• [Documentation] Add Usage examples to online github docs

  documentationenhancementhelp wanted
  intel/rohd-hcl#192 · Filter by author awmoore-intel opened on Mar 17, 2025
  2