From 247a1bcec607ed77a7846fb12dcd6a9c98d730b8 Mon Sep 17 00:00:00 2001 From: rbb666 Date: Thu, 18 Jun 2026 13:36:04 +0800 Subject: [PATCH 1/5] [bsp/rockchip]Add CI compilation checks for RK3500 BSP. --- .github/ALL_BSP_COMPILE.json | 8 ++++++++ .github/workflows/bsp_buildings.yml | 13 ++++++++++++- .../rk3500/.ci/attachconfig/ci.attachconfig.yml | 14 ++++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index ff70275c9e7..9d97520f6c5 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -398,6 +398,14 @@ "zynqmp-a53-dfzu2eg" ] }, + { + "RTT_BSP": "aarch64-bsp-smart", + "RTT_TOOL_CHAIN": "sourcery-aarch64", + "RTT_SMART_TOOL_CHAIN": "aarch64-linux-musleabi", + "SUB_RTT_BSP": [ + "rockchip/rk3500" + ] + }, { "RTT_BSP": "riscv-none", "RTT_TOOL_CHAIN": "sourcery-riscv-none-embed", diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index d3b4968c1ee..312ee717451 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -144,7 +144,7 @@ jobs: echo "RTT_EXEC_PATH=/opt/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64/bin" >> $GITHUB_ENV - name: Install AArch64 ToolChains - if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && success() }} + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && matrix.legs.RTT_SMART_TOOL_CHAIN != 'aarch64-linux-musleabi' && success() }} shell: bash run: | wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.6/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz @@ -153,6 +153,17 @@ jobs: echo "RTT_EXEC_PATH=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin" >> $GITHUB_ENV sudo apt-get -qq install device-tree-compiler + - name: Install AArch64 RT-Smart ToolChains + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && matrix.legs.RTT_SMART_TOOL_CHAIN == 'aarch64-linux-musleabi' && success() }} + shell: bash + run: | + wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu_stable.tar.bz2 + sudo tar xjf aarch64-linux-musleabi_for_x86_64-pc-linux-gnu_stable.tar.bz2 -C /opt + /opt/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin/aarch64-linux-musleabi-gcc --version + echo "RTT_EXEC_PATH=/opt/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin" >> $GITHUB_ENV + echo "RTT_CC_PREFIX=aarch64-linux-musleabi-" >> $GITHUB_ENV + sudo apt-get -qq install device-tree-compiler + - name: Install Mips ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }} shell: bash diff --git a/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml b/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..27c707f3db8 --- /dev/null +++ b/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,14 @@ +scons.args: &scons + scons_arg: + - '--strict' + +devices.spi: + <<: *scons + kconfig: + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_QSPI=y + - CONFIG_RT_USING_DMA=y + - CONFIG_RT_USING_PIN=y + - CONFIG_RT_USING_PINCTRL=y + - CONFIG_RT_SPI_ROCKCHIP=y + - CONFIG_RT_SPI_ROCKCHIP_SFC=y From 78f23f72e3dc291156f94d7ff09a444093f4caaf Mon Sep 17 00:00:00 2001 From: rbb666 Date: Thu, 18 Jun 2026 16:44:37 +0800 Subject: [PATCH 2/5] Adding to the macro definition that was mistakenly deleted in #11477 --- components/drivers/dma/dma-pl330.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/components/drivers/dma/dma-pl330.c b/components/drivers/dma/dma-pl330.c index b0f4bbaa100..8fa207a94d9 100644 --- a/components/drivers/dma/dma-pl330.c +++ b/components/drivers/dma/dma-pl330.c @@ -212,6 +212,27 @@ /** @brief Microcode instruction: write memory barrier */ #define PL330_CMD_DMAWMB 0x13 +/** @brief Microcode instruction sizes */ +#define PL330_SIZE_DMAADDH 3 +#define PL330_SIZE_DMAEND 1 +#define PL330_SIZE_DMAFLUSHP 2 +#define PL330_SIZE_DMALD 1 +#define PL330_SIZE_DMALDP 2 +#define PL330_SIZE_DMALP 2 +#define PL330_SIZE_DMALPEND 2 +#define PL330_SIZE_DMAKILL 1 +#define PL330_SIZE_DMAMOV 6 +#define PL330_SIZE_DMANOP 1 +#define PL330_SIZE_DMARMB 1 +#define PL330_SIZE_DMASEV 2 +#define PL330_SIZE_DMAST 1 +#define PL330_SIZE_DMASTP 2 +#define PL330_SIZE_DMASTZ 1 +#define PL330_SIZE_DMAWFE 2 +#define PL330_SIZE_DMAWFP 2 +#define PL330_SIZE_DMAWMB 1 +#define PL330_SIZE_DMAGO 6 + /** @brief DMAMOV to Source Address Register */ #define PL330_DIR_SAR 0 /** @brief DMAMOV to Channel Control Register */ From 09517dba6e5222c079c111a0e67abc9b688099d4 Mon Sep 17 00:00:00 2001 From: rbb666 Date: Thu, 18 Jun 2026 17:14:49 +0800 Subject: [PATCH 3/5] [bsp/rockchip] Fix RK3528 PLL parent names initialization --- bsp/rockchip/dm/clk/clk-rk-pll.c | 5 +++++ bsp/rockchip/dm/clk/clk-rk-pll.h | 2 +- bsp/rockchip/dm/clk/clk-rk3308.c | 10 +++++----- bsp/rockchip/dm/clk/clk-rk3528.c | 12 ++++++------ bsp/rockchip/dm/clk/clk-rk3568.c | 18 +++++++++--------- bsp/rockchip/rk3300/rtconfig.py | 14 +++++++++++++- bsp/rockchip/rk3500/rtconfig.py | 14 +++++++++++++- 7 files changed, 52 insertions(+), 23 deletions(-) diff --git a/bsp/rockchip/dm/clk/clk-rk-pll.c b/bsp/rockchip/dm/clk/clk-rk-pll.c index c42a460e7c3..69277c85add 100755 --- a/bsp/rockchip/dm/clk/clk-rk-pll.c +++ b/bsp/rockchip/dm/clk/clk-rk-pll.c @@ -1440,6 +1440,11 @@ void rockchip_pll_clk_cell_init(struct rockchip_clk_cell *rk_cell) { struct rockchip_pll_clk_cell *pll_clk_cell = cell_to_rockchip_pll_clk_cell(&rk_cell->cell); + if (rk_cell->cell.parents_nr == 1 && rk_cell->cell.parent_names) + { + rk_cell->cell.parent_name = rk_cell->cell.parent_names[0]; + } + rk_cell->muxdiv_offset = pll_clk_cell->mode_offset; rk_cell->mux_shift = pll_clk_cell->mode_shift; diff --git a/bsp/rockchip/dm/clk/clk-rk-pll.h b/bsp/rockchip/dm/clk/clk-rk-pll.h index 5d718889cb5..df51742bfe1 100755 --- a/bsp/rockchip/dm/clk/clk-rk-pll.h +++ b/bsp/rockchip/dm/clk/clk-rk-pll.h @@ -112,7 +112,7 @@ struct rockchip_pll_clk_cell #define PLL_RAW(_type, _id, _name, _pnames, _pnames_nr, _flags, _con, _mode, _mshift, _lshift, _glock, _pflags, _rtable) \ { \ .rk_cell.cell.name = _name, \ - .rk_cell.cell.parent_names = (void *)_pnames, \ + .rk_cell.cell.parent_names = _pnames, \ .rk_cell.cell.parents_nr = _pnames_nr, \ .rk_cell.cell.flags = RT_CLK_F_GET_RATE_NOCACHE | _flags, \ .rk_cell.id = _id, \ diff --git a/bsp/rockchip/dm/clk/clk-rk3308.c b/bsp/rockchip/dm/clk/clk-rk3308.c index dcce0cbb5fa..f38d17588f4 100755 --- a/bsp/rockchip/dm/clk/clk-rk3308.c +++ b/bsp/rockchip/dm/clk/clk-rk3308.c @@ -154,7 +154,7 @@ static const struct rockchip_cpu_clk_reg_data rk3308_cpu_clk_data = .mux_core_mask = 0x3, }; -PNAME(mux_pll_p) = "xin24m"; +PNAMES(mux_pll_p) = { "xin24m" }; PNAMES(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" }; PNAMES(mux_dpll_vpll0_p) = { "dpll", "vpll0" }; PNAMES(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" }; @@ -216,16 +216,16 @@ static rt_uint32_t uart_src_mux_idx[] = { 3, 4, 0, 1, 2 }; #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) static struct rockchip_pll_clk_cell rk3308_pll_apll = - PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, 1, 0, RK3308_PLL_CON(0), RK3308_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3308_PLL_CON(0), RK3308_MODE_CON, 0, 0, RK3308_GRF_SOC_STATUS0, 0, rk3308_pll_rates); static struct rockchip_pll_clk_cell rk3308_pll_dpll = - PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, 1, 0, RK3308_PLL_CON(8), RK3308_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3308_PLL_CON(8), RK3308_MODE_CON, 2, 1, RK3308_GRF_SOC_STATUS0, 0, rk3308_pll_rates); static struct rockchip_pll_clk_cell rk3308_pll_vpll0 = - PLL_RAW(pll_type_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, 1, 0, RK3308_PLL_CON(16), RK3308_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3308_PLL_CON(16), RK3308_MODE_CON, 4, 2, RK3308_GRF_SOC_STATUS0, 0, rk3308_pll_rates); static struct rockchip_pll_clk_cell rk3308_pll_vpll1 = - PLL_RAW(pll_type_rk3328, PLL_VPLL1, "vpll1", mux_pll_p, 1, 0, RK3308_PLL_CON(24), RK3308_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_VPLL1, "vpll1", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3308_PLL_CON(24), RK3308_MODE_CON, 6, 3, RK3308_GRF_SOC_STATUS0, 0, rk3308_pll_rates); static struct rockchip_clk_cell rk3308_uart0_fracmux = diff --git a/bsp/rockchip/dm/clk/clk-rk3528.c b/bsp/rockchip/dm/clk/clk-rk3528.c index c77e74d3602..65c61c4bed1 100755 --- a/bsp/rockchip/dm/clk/clk-rk3528.c +++ b/bsp/rockchip/dm/clk/clk-rk3528.c @@ -160,7 +160,7 @@ static const struct rockchip_cpu_clk_reg_data rk3528_cpu_clk_data = .mux_core_mask = 0x1, }; -PNAME(mux_pll_p) = "xin24m"; +PNAMES(mux_pll_p) = { "xin24m" }; PNAMES(mux_24m_32k_p) = { "xin24m", "clk_32k" }; PNAMES(mux_gpll_cpll_p) = { "gpll", "cpll" }; PNAMES(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; @@ -200,19 +200,19 @@ PNAMES(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" }; #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) static struct rockchip_pll_clk_cell rk3528_pll_apll = - PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(0), RK3528_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(0), RK3528_MODE_CON, 0, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); static struct rockchip_pll_clk_cell rk3528_pll_cpll = - PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(8), RK3528_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(8), RK3528_MODE_CON, 2, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); static struct rockchip_pll_clk_cell rk3528_pll_gpll = - PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(24), RK3528_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(24), RK3528_MODE_CON, 4, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); static struct rockchip_pll_clk_cell rk3528_pll_ppll = - PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), RK3528_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), RK3528_MODE_CON, 6, 0, RK3528_GRF_SOC_STATUS0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates); static struct rockchip_pll_clk_cell rk3528_pll_dpll = - PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, 1, RT_CLK_F_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), RK3528_DDRPHY_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), RK3528_DDRPHY_MODE_CON, 0, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); static struct rockchip_clk_cell rk3528_uart0_fracmux = diff --git a/bsp/rockchip/dm/clk/clk-rk3568.c b/bsp/rockchip/dm/clk/clk-rk3568.c index 90ca38fe5c1..33c78ae7acf 100755 --- a/bsp/rockchip/dm/clk/clk-rk3568.c +++ b/bsp/rockchip/dm/clk/clk-rk3568.c @@ -264,7 +264,7 @@ static const struct rockchip_cpu_clk_reg_data rk3568_cpu_clk_data = .mux_core_mask = 0x1, }; -PNAME(mux_pll_p) = "xin24m"; +PNAMES(mux_pll_p) = { "xin24m" }; PNAMES(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; PNAMES(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; PNAMES(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; @@ -375,29 +375,29 @@ PNAMES(i2s3_mclk_ioe_p) = { "i2s3_mclkin", "i2s3_mclkout" }; #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) static struct rockchip_pll_clk_cell rk3568_pmu_pll_ppll = - PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, 1, 0, RK3568_PMU_PLL_CON(0), RK3568_PMU_MODE_CON0, + PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PMU_PLL_CON(0), RK3568_PMU_MODE_CON0, 0, 4, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates); static struct rockchip_pll_clk_cell rk3568_pmu_pll_hpll = - PLL_RAW(pll_type_rk3328, PLL_HPLL, "hpll", mux_pll_p, 1, 0, RK3568_PMU_PLL_CON(16), RK3568_PMU_MODE_CON0, + PLL_RAW(pll_type_rk3328, PLL_HPLL, "hpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PMU_PLL_CON(16), RK3568_PMU_MODE_CON0, 2, 7, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates); static struct rockchip_pll_clk_cell rk3568_pll_apll = - PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, 1, 0, RK3568_PLL_CON(0), RK3568_MODE_CON0, + PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(0), RK3568_MODE_CON0, 0, 0, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates); static struct rockchip_pll_clk_cell rk3568_pll_dpll = - PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, 1, 0, RK3568_PLL_CON(8), RK3568_MODE_CON0, + PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(8), RK3568_MODE_CON0, 2, 1, RK3568_GRF_SOC_STATUS0, 0, RT_NULL); static struct rockchip_pll_clk_cell rk3568_pll_cpll = - PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, 1, 0, RK3568_PLL_CON(24), RK3568_MODE_CON0, + PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(24), RK3568_MODE_CON0, 4, 2, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates); static struct rockchip_pll_clk_cell rk3568_pll_gpll = - PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, 1, 0, RK3568_PLL_CON(16), RK3568_MODE_CON0, + PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(16), RK3568_MODE_CON0, 6, 3, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates); static struct rockchip_pll_clk_cell rk3568_pll_npll = - PLL_RAW(pll_type_rk3328, PLL_NPLL, "npll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3568_PLL_CON(32), RK3568_MODE_CON0, + PLL_RAW(pll_type_rk3328, PLL_NPLL, "npll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3568_PLL_CON(32), RK3568_MODE_CON0, 10, 5, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates); static struct rockchip_pll_clk_cell rk3568_pll_vpll = - PLL_RAW(pll_type_rk3328, PLL_VPLL, "vpll", mux_pll_p, 1, 0, RK3568_PLL_CON(40), RK3568_MODE_CON0, + PLL_RAW(pll_type_rk3328, PLL_VPLL, "vpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(40), RK3568_MODE_CON0, 12, 6, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates); static struct rockchip_clk_cell rk3568_i2s0_8ch_tx_fracmux = diff --git a/bsp/rockchip/rk3300/rtconfig.py b/bsp/rockchip/rk3300/rtconfig.py index 5ae06181dcd..4ce428c3793 100755 --- a/bsp/rockchip/rk3300/rtconfig.py +++ b/bsp/rockchip/rk3300/rtconfig.py @@ -1,4 +1,5 @@ import os +import subprocess # toolchains options ARCH ='aarch64' @@ -34,11 +35,22 @@ OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' + def _ld_option_supported(ld_path, option): + try: + return subprocess.call([ld_path, option], + stdout=subprocess.DEVNULL, + stderr=subprocess.DEVNULL) == 0 + except OSError: + return False + + _ld_path = os.path.join(EXEC_PATH, PREFIX + 'ld') + _ldflags_rwx = ' -Wl,--no-warn-rwx-segments' if _ld_option_supported(_ld_path, '--no-warn-rwx-segments') else '' + DEVICE = ' -g -march=armv8-a -mtune=cortex-a35 -fdiagnostics-color=always' CPPFLAGS= ' -nostdinc -undef -E -P -x assembler-with-cpp' CFLAGS = DEVICE + ' -Wall -Wno-cpp' AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' - LFLAGS = DEVICE + ' -nostartfiles -Wl,--no-warn-rwx-segments -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + LFLAGS = DEVICE + ' -nostartfiles' + _ldflags_rwx + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' CPATH = '' LPATH = '' diff --git a/bsp/rockchip/rk3500/rtconfig.py b/bsp/rockchip/rk3500/rtconfig.py index 70773ac7bce..853466248e3 100644 --- a/bsp/rockchip/rk3500/rtconfig.py +++ b/bsp/rockchip/rk3500/rtconfig.py @@ -1,4 +1,5 @@ import os +import subprocess # toolchains options ARCH ='aarch64' @@ -34,6 +35,17 @@ OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' + def _ld_option_supported(ld_path, option): + try: + return subprocess.call([ld_path, option], + stdout=subprocess.DEVNULL, + stderr=subprocess.DEVNULL) == 0 + except OSError: + return False + + _ld_path = os.path.join(EXEC_PATH, PREFIX + 'ld') + _ldflags_rwx = ' -Wl,--no-warn-rwx-segments' if _ld_option_supported(_ld_path, '--no-warn-rwx-segments') else '' + # For Cortex-A55/A76 # DEVICE = ' -g -march=armv8.2-a -mtune=cortex-a55 -fdiagnostics-color=always' # For Cortex-A53/A72 @@ -41,7 +53,7 @@ CPPFLAGS= ' -nostdinc -undef -E -P -x assembler-with-cpp' CFLAGS = DEVICE + ' -Wall -Wno-cpp' AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' - LFLAGS = DEVICE + ' -nostartfiles -Wl,--no-warn-rwx-segments -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + LFLAGS = DEVICE + ' -nostartfiles' + _ldflags_rwx + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' CPATH = '' LPATH = '' From 4db40702a37dd167d2dc755b41e177180b8000ef Mon Sep 17 00:00:00 2001 From: Rbb666 Date: Sun, 21 Jun 2026 12:15:56 +0800 Subject: [PATCH 4/5] [bsp][rockchip] Fix dist packaging for shared dm drivers --- bsp/rockchip/rk3300/rtconfig.py | 6 ++++++ bsp/rockchip/rk3500/rtconfig.py | 6 ++++++ bsp/rockchip/tools/sdk_dist.py | 30 ++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+) create mode 100644 bsp/rockchip/tools/sdk_dist.py diff --git a/bsp/rockchip/rk3300/rtconfig.py b/bsp/rockchip/rk3300/rtconfig.py index 4ce428c3793..a7da6775ada 100755 --- a/bsp/rockchip/rk3300/rtconfig.py +++ b/bsp/rockchip/rk3300/rtconfig.py @@ -64,3 +64,9 @@ def _ld_option_supported(ld_path, option): DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/rockchip/rk3500/rtconfig.py b/bsp/rockchip/rk3500/rtconfig.py index 853466248e3..c3b64286789 100644 --- a/bsp/rockchip/rk3500/rtconfig.py +++ b/bsp/rockchip/rk3500/rtconfig.py @@ -70,3 +70,9 @@ def _ld_option_supported(ld_path, option): DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' POST_ACTION += 'md5sum rtthread.bin\n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/rockchip/tools/sdk_dist.py b/bsp/rockchip/tools/sdk_dist.py new file mode 100644 index 00000000000..bbd7c2626c4 --- /dev/null +++ b/bsp/rockchip/tools/sdk_dist.py @@ -0,0 +1,30 @@ +import os + + +def update_dm_paths(dm_dir, dist_dir): + components_dir = os.path.join(dist_dir, 'rt-thread', 'components') + + for root, dirs, files in os.walk(dm_dir): + if 'SConscript' not in files: + continue + + sconscript_path = os.path.join(root, 'SConscript') + component_path = os.path.relpath(components_dir, root).replace(os.path.sep, '/') + with open(sconscript_path, 'r') as f: + data = f.read() + + data = data.replace('../../../../components', component_path) + + with open(sconscript_path, 'w') as f: + f.write(data) + + +def dist_do_building(BSP_ROOT, dist_dir): + from mkdist import bsp_copy_files + + dm_dir = os.path.join(os.path.dirname(dist_dir), 'dm') + + print("=> copy rockchip dm") + bsp_copy_files(os.path.join(os.path.dirname(BSP_ROOT), 'dm'), + dm_dir) + update_dm_paths(dm_dir, dist_dir) From 935b5c27ceee1b1b920e7450b44631bc908bb4f5 Mon Sep 17 00:00:00 2001 From: Rbb666 Date: Sun, 21 Jun 2026 16:09:54 +0800 Subject: [PATCH 5/5] [bsp][rockchip] Add rk3500 DM driver CI coverage --- .../.ci/attachconfig/ci.attachconfig.yml | 73 ++++++++++++++++++- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml b/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml index 27c707f3db8..527ba38637e 100644 --- a/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml @@ -2,13 +2,80 @@ scons.args: &scons scons_arg: - '--strict' -devices.spi: +devices.dm.all: <<: *scons kconfig: + - CONFIG_RT_USING_DM=y + - CONFIG_RT_USING_OFW=y + - CONFIG_RT_USING_RESET=y + - CONFIG_RT_USING_PIN=y + - CONFIG_RT_USING_PINCTRL=y + - CONFIG_RT_USING_CLK=y + - CONFIG_RT_USING_REGULATOR=y + - CONFIG_RT_USING_PIC=y + - CONFIG_RT_USING_MFD=y + - CONFIG_RT_MFD_SYSCON=y + - CONFIG_RT_MFD_RK8XX=y + - CONFIG_RT_USING_ADC=y + - CONFIG_RT_ADC_ROCKCHIP_SARADC=y + - CONFIG_RT_USING_CAN=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_CANFD_ROCKCHIP=y + - CONFIG_RT_USING_CLOCK_TIME=y + - CONFIG_RT_CLOCK_TIMER_ROCKCHIP=y + - CONFIG_RT_USING_I2C=y + - CONFIG_RT_I2C_RK3X=y + - CONFIG_RT_USING_PWM=y + - CONFIG_RT_PWM_ROCKCHIP=y + - CONFIG_RT_USING_RTC=y + - CONFIG_RT_RTC_RK8XX=y + - CONFIG_RT_RTC_RK_TIMER=y + - CONFIG_RT_USING_SDIO=y + - CONFIG_RT_SDIO_DW_MMC=y + - CONFIG_RT_SDIO_DW_MMC_ROCKCHIP=y - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_QSPI=y - CONFIG_RT_USING_DMA=y - - CONFIG_RT_USING_PIN=y - - CONFIG_RT_USING_PINCTRL=y - CONFIG_RT_SPI_ROCKCHIP=y - CONFIG_RT_SPI_ROCKCHIP_SFC=y + - CONFIG_RT_USING_WDT=y + - CONFIG_RT_WDT_RK8XX=y + - CONFIG_RT_USING_HWCRYPTO=y + - CONFIG_RT_HWCRYPTO_USING_RNG=y + - CONFIG_RT_HWCRYPTO_RNG_ROCKCHIP=y + - CONFIG_RT_USING_INPUT=y + - CONFIG_RT_INPUT_MISC=y + - CONFIG_RT_INPUT_MISC_PWRKEY_RK8XX=y + - CONFIG_RT_USING_MBOX=y + - CONFIG_RT_MBOX_ROCKCHIP=y + - CONFIG_RT_USING_HWSPINLOCK=y + - CONFIG_RT_HWSPINLOCK_ROCKCHIP=y + - CONFIG_RT_USING_PHYE=y + - CONFIG_RT_PHYE_ROCKCHIP_NANENG_COMBO=y + - CONFIG_RT_PHYE_ROCKCHIP_SNPS_PCIE3=y + - CONFIG_RT_MFD_RK8XX_I2C=y + - CONFIG_RT_MFD_RK8XX_SPI=y + - CONFIG_RT_REGULATOR_RK8XX=y + - CONFIG_RT_PMDOMAIN_ROCKCHIP=y + - CONFIG_RT_USING_THERMAL=y + - CONFIG_RT_THERMAL_ROCKCHIP_TSADC=y + - CONFIG_RT_USING_NVMEM=y + - CONFIG_RT_NVMEM_ROCKCHIP_OTP=y + - CONFIG_RT_USING_PCI=y + - CONFIG_RT_PCI_DW=y + - CONFIG_RT_PCI_DW_ROCKCHIP=y + - CONFIG_RT_PIN_ROCKCHIP=y + - CONFIG_RT_PINCTRL_ROCKCHIP_RK8XX=y + - CONFIG_RT_PINCTRL_ROCKCHIP=y + - CONFIG_RT_CLK_ROCKCHIP_RK8XX_CLKOUT=y + - CONFIG_RT_CLK_ROCKCHIP_LINK=y + - CONFIG_RT_CLK_ROCKCHIP=y + - CONFIG_RT_CLK_ROCKCHIP_RK3308=y + - CONFIG_RT_CLK_ROCKCHIP_RK3528=y + - CONFIG_RT_CLK_ROCKCHIP_RK3568=y + - CONFIG_RT_CLK_ROCKCHIP_RK3576=y + - CONFIG_RT_CLK_ROCKCHIP_RK3588=y + - CONFIG_RT_SOC_ROCKCHIP_FIQ_DEBUGGER=y + - CONFIG_RT_SOC_ROCKCHIP_GRF=y + - CONFIG_RT_SOC_ROCKCHIP_HW_DECOMPRESS=y + - CONFIG_RT_SOC_ROCKCHIP_IODOMAIN=y